What are understood by smart power ICs are integrated circuit arrangements that comprise a combination of power ICs and an "intelligent part" that comprises logic modules or sensor modules or the like. Whereas the power ICs are usually operated with higher voltages above 100 volts, usually around 500 volts, the intelligent part comprises low-voltage components that are operated at voltage levels around 5 volts. It is therefore necessary to electrically separate the power ICs from the low-voltage components. For example, MOSFETs, IGBTs (insulated gate bipolar transistor), MCT (MOS controlled thyristor) and the like are employed as power ICs.
The insulation between power ICs and the low-voltage components should avoid disturbances in the intelligent part due to electrical fields and/or minority carrier injection, optimally preventing these. This insulation is often realized as a dielectric insulation.
For this purpose, I. Nakagawa, ISPSD 91, p. 16 discloses that the dielectric insulation be produced on an SOI substrate that is manufactured according to the DWB (direct wafer bonding) or SDB (silicon wafer direct bonding) method. The components are realized in the silicon layer of the SOI substrate. The individual components are insulated from one another by an insulating trench that completely surrounds the respective component and that extends to the insulating layer of the SOI substrate. Both power components as well as low-voltage components are provided next to one another in the silicon layer of the SOI substrate. The component area is thus composed of the respective areas occupied by the power component and by the intelligent part. There is also the risk of a disturbance of the intelligent part due to capacitative influences.
B. Mutterlein et al., Proc. ESSDERC 93, pp. 879-882 discloses that power components and low-voltage components are integrated in a substrate, whereby oxygen is locally implanted in the region of the low-voltage components for insulation between the power components and the low-voltage components, an SIMOX substrate thus arising. The area requirements of the resulting circuit given this technique are likewise equal to the sum of the areas of the sub-circuits. Capacitative disturbances on the low-voltage components are even more pronounced here.
Cahill et al., ECS 89, p. 324 (1989) discloses that power components are realized in a silicon substrate. Neighboring power components are insulated from one another by field oxide regions that, for example, are manufactured in a LOCOS process. Subsequently, the surface of the substrate is provided with an insulating layer. A polysilicon layer that is recrystallized by zone melting is applied on the insulating layer. Thin-film MOS transistors are realized in the recrystallized silicon layer. The thin-film MOS transistors are arranged above the field oxide regions between the power component. Here, too, the area requirements are composed of the area for the intelligent part and the area for the power part.
F. Robb et al., ECS 92 Conference Proc. p. 467 and G. M. Dolny et al., IEDM 92 Conf. Proc., p. 233 disclose that power components are integrated in a silicon substrate and MOS thin-film transistors are realized in a polycrystalline silicon layer for the intelligent part. The polysilicon layer is arranged above insulation regions that separate the power components in the substrate. The thin-film transistors are then arranged above these insulation regions. In particular, it is possible to realize the thin-film transistors in the same polysilicon layer from which the gate electrodes for the power components are manufactured. The areas for the power components and the area for the intelligent part define the area of the component as a sum.
Nakashima et al., Electronics Lett. 19, p. 1095 (1983) discloses that high-voltage CMOS transistors are manufactured with a buried channel in an SIMOX substrate. For that purpose, a buried SiO.sub.2 layer is formed by implantation of oxygen. In the same implantation step, a layer that shields the electrical field (electric field shielding layer) is formed between the SiO.sub.2 layer and the transistor region by controlling the particle current during the implantation.